The present invention relates to a multi-CPU (Central Processing Unit) system with a common memory in which, in using the common memory data information is transferred between plural CPUs. More particularly, it relates to control of the common memory.
A multi-CPU system in which, in using a common memory, data information is mutually transferred between plural CPUs is well known in the prior art technology. Two typical examples are disclosed in Japanese Patent Application Laid-Open No. 243763/1985 and Japanese Patent Application Laid-Open No. 245063/1985.
In FIG. 10, the multi-CPU system disclosed in the Japanese Patent Application Laid-Open No. 243763/1985 is illustrated. In this system, data information is mutually transferred between a word CPU 1 which accesses a common memory 3 with one word length unit and a byte CPU 2 which accesses the same common memory 3 with one byte length unit. The length of one byte is equal to one half of the length of one word. The common memory 3 comprises two dual port memories 3.sub.1 and 3.sub.2, each storing data information of one byte. In this multi-CPU system, when data information of one word length is written into the common memory 3 from the byte CPU 2, the first one byte of the data information of one word length is stored in one of the dual port memories, for example 3.sub.1 , and then the second one byte of the data information is stored in the other dual port memory 3.sub.2. However, during these two processes of operation, contention of access may happen when the word CPU 1 accesses the common memory 3 while the byte CPU 2 continues writing the second one byte of the data information into the same address. This contention of access may destroy the data information of one word to be inputted to the common memory 3 from the byte CPU 2 or may causes the word CPU 1 to read incorrect data information with renewed data of only one byte. On the contrary, when data information of one word is read from the common memory 3 to the byte CPU 2, the first one byte of the data information of one word is read out firstly, and then the second one byte of the data information is read out. In this case too, during these two processes of operation, contention of access may happen when the word CPU 1 writes new data information into the common memory 3 while the byte CPU 2 continues reading the second one byte of the data information from the same address. This contention of access may destroy the data information to be outputted from the common memory 3 to the byte CPU 2.
Considering these facts, in this prior art multi-CPU system, the word CPU 1 is prohibited from accessing the common memory 3 and is kept in its waiting state at least while the byte CPU 2 is accessing the common memory 3 for data information of one word. The word "at least" means that the contention problem is "at least" avoided by the above stated technique. Actually, in the prior art multi-CPU system of FIG. 10, even the byte CPU 2 is prohibited from accessing the common memory 3 and is kept in its waiting state while the word CPU 1 is accessing the common memory 3. More specifically, when both the word CPU 1 and the byte CPU 2 access the common memory 3, access demand signals S1 and S2 from the respective CPUs are supplied to respective input terminals of an interlock circuit 20 which consists of a flip-flop circuit. A "NAND" result of output signals from the interlock circuit 20 allows either the word CPU 1 or the byte CPU 2 to get access to the common memory 3. Herein, the access demand signal S2 from the word CPU 1 is subjected to an "AND" operation with an inversion of a word access signal S3 which is outputted when the byte CPU 2 accesses for data information of one word, and the AND result is supplied to the interlock circuit 20. Hence, while the byte CPU 2 accesses the common memory 3 for the data information of one word, the access demand signal S2 from the word CPU 1 cannot be inputted to the interlock circuit 20. That is, while the byte CPU 2 continues accessing the common memory 3 for the second one byte, the word CPU 1 cannot access the common memory 3. Inverted signals of the outputs from the interlock circuit 20 and the respective access demand signals S1 and S2 are subjected to an AND operation to form respective waiting signals S4 and S5. By virtue of these waiting signals S4 and S5, while one CPU is accessing the common memory, the other CPU is kept in its waiting state. As was described above, this kind of multi-CPU system assures the data information of one word in the common memory 3 when the byte CPU 2 accesses that information.
However, in this kind of multi-CPU system, while one CPU is accessing a certain address, the other CPU is kept in its waiting state even if it requests access to another address. This results in longer information processing time.
In FIG. 11, the multi-CPU system disclosed in Japanese Patent Application Laid-Open No. 245063/1985 is illustrated. The purpose of this prior art is to improve the problem of the prior art system of FIG. 10 which requires longer time in data transfer operations. In this multi-CPU system, time periods in which two CPUs 1 and 2 asynchronously access a memory 3 are alternately assigned to the two CPUs. The system allows the CPU 1, for example, to access the common memory 3 only during the period which is assigned to the CPU 1 to access the common memory 3. This multi-CPU system comprises: a pulse generator 21 which generates continuous pulse signals; a flip-flop 22 which is alternately set and reset by an output signal from the pulse generator 21, AND gates 23 and 24 which take "AND" operations between respective output signals from the flip-flop 22 and respective access demand signals A and B from the CPUs 1 and 2; flip-flops 25 and 26 which ar set by respective output signals from the AND gates 23 and 24; and an address selector 27 which allows one of the CPUs to access its designated address according to which of the flip-flops 25 and 26 is in its set condition. That is, if the access demand signals A and B are outputted from the respective CPUs 1 and 2 when one of outputs Q and Q of the flip-flop 22 which correspond to the respective CPUs 1 and 2 has a high-level value, one of the flip-flops 25 and 26 is set and the corresponding CPU 1 or 2 is allowed to access the designated address which is latched in the CPU 1 or 2. Herein the CPUs 1 and 2 have their address latches as peripheral circuits in order to latch the address to access. Moreover, the inverted output Q from each of flip-flops 25 and 26 is supplied to an "inhibition" terminal of the AND gate 23 or 24 which is connected to the other flip-flop 25 or 26 in order to inhibit one CPU from accessing the common memory 3 while the other CPU is accessing that. Furthermore, when one access has been completed, the flip-flops 25 and 26 are reset by respective notice signals E1 and E2 which are outputted from respective CPUs 1 and 2. In this multi-CPU system, since the waiting loss time occurs only when the CPU fails to access in the period assigned to that CPU, the data transfer time is shorter than the previous multi-CPU system. However, even in this multi-CPU system, while one CPU is accessing the common memory 3, the other CPU is kept in its waiting state even if the other CPU requests access to a different address. There still exists a problem of extra processing time.
Another technique is disclosed in the prior art multi-CPU system using a common memory which is a dual port memory comprising a "busy" terminal as a contention mediation terminal from which a mediation signal is outputted on the occasion of access contention in order to keep one CPU in its waiting state only while the other CPU is accessing the same address of the common memory. For this kind of common memory with the busy terminal, for example, MB8421 made by Fujitsu, Ltd. is employable. In this common memory for the multi-CPU system, when the addresses and chip selection signals (CS) of the CPUs contend with each other, the common memory gives a priority to the CPU which accessed the common memory earlier, and it keeps the other CPU in its waiting state by keeping the corresponding busy signal (Busy) at the low level. In FIG. 12, an example of a multi-CPU system utilizing this kind of common memory is illustrated. In this system, the data information is mutually transferred between CPUs 1 and 2 through a common memory 3. For the aforesaid CPUs 1 and 2, for example, Intel 8085 and 8086 type are employed. This type of CPU has a "Ready" terminal whose state is changed to the high level when it can access. By connecting this Ready terminal to the Busy terminal of the common memory 3, this system can easily realize the contention mediation to the common memory 3. That is, when the CPU 2 requests access to the common memory 3 while the CPU 1 is accessing the same address of that, the common memory 3 makes the Busy signal (Busy.sub.2) take the low level and thereby keeps the CPU 2 in its waiting state until completion of the access from the CPU 1. The CPU 2 can access the common memory 3 after the access from the CPU 1 has been completed and the busy signal (Busy.sub.2) has changed to the high level. As was described above, the contention mediation to the same address of the common memory 3 can be realized. Herein, a control signal (Cnt) in FIG. 12 includes signals such as a read signal (RD), a write signal (WT) and a chip selection signal (CS).
However, heretofore, since the so called "one-chip microcomputer" such as an Intel 8031 type does not have the Ready terminal or an equivalent terminal, it cannot perform the above stated contention mediation to the common memory 3.